1. Technical Field
This invention generally relates to semiconductor fabrication, and more specifically relates to interconnects in semiconductor fabrication.
2. Background Art
Modern VLSI semiconductor processing allows for the creation of millions of devices fabricated on a single wafer. To connect these devices, VLSI designs use electrically conductive lines. These interconnection lines are typically on several different layers, generally referred to as metal layer 1, metal layer 2, etc. The interconnection lines are generally connected to other interconnection lines above or below with various types of interlevel interconnection structures, commonly referred to as studs. Several different technologies exist for making these studs. Interconnect studs generally use a separate metal interconnect level to connect layers where other technologies may use tapered vias (i.e., tapered openings in the insulator separating the metal layers to form the connection). Interconnect studs have become popular because their structure has allowed for greater scaling and thus greater device density.
Turning to FIG. 5, a semiconductor portion 800 is illustrated. In the portion 800, a interconnection stud 802 connects between a first connection line 804 and a second connection line 806. The interconnection stud 802 generally consists of a tungsten (W) core 801 with a titanium/titanium nitride (Ti/TiN) liner 808, although other suitable materials are sometimes used.
Ideally, the interconnection stud 802 would be lined up directly with first connection line 804 and second connection line 806. However, mask to wafer misalignments generally introduce some amount of offset between the stud 802 and the connection lines 804 and 806. This is generally acceptable as long as there remains sufficient connection between studs and connection lines.
The first and second connection lines 804 and 806 generally consist of a metal with high conductivity, such as aluminum copper (AlCu), copper (Cu) or another conductor, such as polysilicon. Aluminum copper is generally chosen because of its good conductivity. It is also advantageous because patterning AlCu is relatively easy, i.e., deposit and reactive ion etch (RIE), or otherwise directional etch.
The connection line 804 is generally fabricated by first depositing a blanket of AlCu, followed by a blanket deposition of titanium 810. Photoresist is then applied, exposed and developed, leaving patterns of photoresist on the blanket of titanium and AlCu. Reactive ion etch is then used to etch away the Ti/AlCu everywhere the photoresist is developed away. The reactive ion etch uses chlorine bases ions that chemically react and physically bombard the Ti/AlCu, leaving only the portions of the Ti/AlCu that were covered by photoresist.
One side effect of the reactive ion etch is that a polymer film 814 is formed on the sidewalls of the Ti/AlCu. This is caused by the degrading of the photoresist that occurs during reactive ion etching. The photoresist generally contains carbon, which combines with the atoms in the etch process to form carbonized polymer atoms, which deposit themselves on the sidewalls of the Ti/AlCu. These polymer films 814 (illustrated as dark lines) do not etch, and become a type of sidewall mask. This polymer film has the advantage of the preventing the chlorine gas from isotropically etching into the sides of the near vertical Ti/AlCu metal lines eliminating the possibility of undercuts in the interconnections lines.
Although AlCu has several advantages, it also has the disadvantage of being susceptible to electro-migration. When enough current is applied to AlCu electro-migration can cause voids to be formed in the AlCu line. If these voids are large enough, open circuits can be formed.
This is one reason why the titanium layer 810 is formed above the AlCu connection line 804. The titanium layer serves to hold the line together and provides an alternative current path where voids have caused opens to form in the AlCu line. Titanium has a relatively poor conductivity when compared to AlCu, but it can conduct much more current before it starts to electro-migrate. Thus, the titanium layer 810 increases the life of the AlCu connection line 804.
The connection line 804 is connected to the connection line 806 through interconnect stud 802. Interconnect studs can be used in greater densities than other techniques, such as the use of tapered vias that are filled with metal as part of the next metal layer.
Interconnect studs typically use tungsten as a fill material. Tungsten is used because it can be deposited by using chemical vapor deposition (CVD) into a near vertical hole to form a stud. Other materials, such as AlCu that are deposited by sputtering or evaporation are not used for interconnect studs because of their propensity to create voids when deposited in a hole. After Ti/AlCu connection line 804 is formed, an insulator, such as silicon dioxide (SiO.sub.2) or polymide, is blanket deposited and is then planerized by CMP, as shown by line 815. A stud opening or hole is formed in the insulator, exposing an opening to the interconnection line 804, by the technique of applying photoresist, exposing and developing openings in the photoresist, RIE of the insulator, and the removing the unwanted photoresist left in an O.sub.2 plasma wash.
Next, the stud 802 is formed by first sputtering a thin titanium/titanium nitride (Ti/TiN) layer 808 into the hole. The Ti/TiN layer 808 is formed to prevent the fluorine of the tungsten CVD process from reacting with the titanium and forming TiF.sub.3, a very high resistance material. Next, tungsten is chemical vapor deposited into the hole, filling the hole. A chemical mechanical polish (CMP) is used to polish back the tungsten to be planar.
The second connection line 806 is then formed in the same manner as the first connection line 804. Thus, the first and second connection lines 804 and 806 are connected together with the tungsten interconnect stud 802. Unfortunately, there are disadvantages to this system. In particular, the polymer films 814 act as an insulator. Thus, the only electrical connection between the tungsten stud 802 and the first interconnection line 804 is through the Ti/TiN layer 808 and the top of the titanium layer 810 at region 816.
In the case of misalignment only a portion of the Ti/TiN layer 808 is in contact with a portion of the Ti layer 810 in region 816. Additionally, both Ti and TiN have relatively poor conductivity. This is generally acceptable in the prior art because the layers are relatively thin. However, the low conductivity combined with misalignment will be a problem as the density of semiconductor devices increases and the connection areas become smaller. All of these factors increase the resistance of the connection and will eventually reach a point where there is insufficient conduction between connections.
Thus, what is needed is a method and structure to facilitate interconnection between connection lines and interconnect studs such that sufficiently conductive interconnects are assured as device sizes decrease.